Semiconductor package with enhanced electrical and thermal performance and method for fabricating the same

ABSTRACT

A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a divisional of copending application U.S. Ser. No.10/157,069, now U.S. Pat. No. 6,703,698 filed on May 29, 2002.

FIELD OF THE INVENTION

The present invention relates to semiconductor packages and fabricationmethods thereof, and more particularly, to a BGA (ball grid array)package with enhanced electrical and thermal performance, and a methodfor fabricating the BGA package.

BACKGROUND OF THE INVENTION

BGA (ball grid array) is an advanced type of semiconductor packagingtechnology, which is characterized by the use of a substrate as a chipcarrier whose front surface is used for mounting one or moresemiconductor chips and whose back surface is provided with a pluralityof array-arranged solder balls. During a SMT (surface mount technology)process, a BGA package can be mechanically bonded and electricallycoupled to an external device such as a printed circuit board (PCB) bymeans of these solder balls.

Patents related to BGA technology include, for example, U.S. Pat. No.5,851,337 entitled “METHOD OF CONNECTING TEHS ON PBGA AND MODIFIEDCONNECTING STRUCTURE”. This patent is characterized by the use of aground circuit for connecting a heat spreader to a substrate to helpenhance grounding effect of a BGA package. One drawback to this patent,however, is that it is unsuitably used for packaging semiconductor chipshaving a great number of power and ground pads.

A conventional solution to the foregoing problem is depicted withreference to FIGS. 1A and 1B. As shown, an exemplified BGA packagecomprises: a substrate 100, at least a semiconductor chip 110, apower-connecting heat spreader 120, a ground-connecting heat spreader130, a plurality of sets of bonding wires 141, 142, 143, anencapsulation body 150, and a plurality of array-arranged solder balls160.

The substrate 100 has a front surface 100 a and a back surface 100 a andis formed with a plurality of electrically-conductive vias 101 a, 101 b,101 c at predetermined positions, including power vias 101 a, groundvias 101 b and I/O (input/output) vias 101 c, which are adapted topenetrate through the substrate 100.

The semiconductor chip 110 has an active surface 110 a and an inactivesurface 110 b. The active surface 110 a is formed with a plurality ofbond pads 111 a, 111 b, 111 c, including power pads 111 a, ground pads111 b and I/O pads 111 c. This active surface 110 a of the semiconductorchip 110 is further formed with a power plane 112 a and a ground plane112 b, wherein the power plane 112 a is electrically connected to thepower pads 111 a by a first set of bonding wires 141, and the groundplane 112 b is electrically connected to the ground pads 111 b by asecond set of bonding wires 142. Further, the I/O pads 111 c areelectrically connected by a third set of bonding wires 143 to the I/Ovias 101 c on the front surface 100 a of the substrate 100.

The power-connecting heat spreader 120 is integrally formed by a supportportion 121, an overhead portion 122 and a downward-extending portion123. The power-connecting heat spreader 120 is mounted over thesubstrate 100 to partly cover the semiconductor chip 110, wherein thesupport portion 121 is electrically bonded to the power vias 101 a ofthe substrate 100, and the downward-extending portion 123 iselectrically bonded to the power plane 112 a on the semiconductor chip110, allowing the overhead portion 122 to be elevated in position abovethe semiconductor chip 110 by the support portion 121 and thedownward-extending portion 123. The power-connecting heat spreader 120is used to connect power to the semiconductor chip 110, and to dissipateheat generated by the semiconductor chip 110 during operation.

Similarly, the ground-connecting heat spreader 130 is composed of asupport portion 131, an overhead portion 132 and a downward-extendingportion 133. The ground-connecting heat spreader 130 is mounted over thesubstrate 100 to partly cover the semiconductor chip 110, wherein thesupport portion 131 is electrically bonded to the ground vias 101 b ofthe substrate 100, and the downward-extending portion 133 iselectrically bonded to the ground plane 112 b on the semiconductor chip110, allowing the overhead portion 132 to be elevated in position abovethe semiconductor chip 110 by the support portion 131 and thedownward-extending portion 133. The ground-connecting heat spreader 130is used to connect the semiconductor chip 110 to ground, and todissipate heat generated by the semiconductor chip 110 during operation.

The encapsulation body 150 is formed to encapsulate the front surface100 a of the substrate 100, the semiconductor chip 110, thepower-connecting heat spreader 120, and the ground-connecting heatspreader 130. In view of power transmission and grounding purposes, thepower-connecting heat spreader 120 and the ground-connecting heatspreader 130 are preferably not exposed to outside of the encapsulationbody 150.

The array-arranged solder balls 160 are implanted on the back surface100 b of the substrate 100, including a plurality of power balls 161electrically connected to the power vias 101 a, a plurality of groundballs 162 electrically connected to the ground vias 101 b, and aplurality of I/O balls 163 electrically connected to the I/O vias 101 c.

By the above structure as illustrated in FIG. 1A, power can beexternally supplied to the semiconductor chip 110 successively via thepower balls 161, the power vias 101 a, the power-connecting heatspreader 120, the power plane 112 a, the bonding wires 141, and thepower pads 111 a. Moreover, the semiconductor chip 110 can be connectedto ground successively via the ground pads 111 b, the bonding wires 142,the ground plane 112 b, the ground-connecting heat spreader 130, theground vias 101 b, and the ground balls 162. Further, the semiconductorchip 110 can transfer I/O signals via the I/O pads 111 c, the bondingwires 143, the I/O vias 101 c, and the I/O balls 163.

One drawback to the forgoing BGA package, however, is that, since theground-connecting heat spreader 130 only covers part of thesemiconductor chip 110, it would not be able to provide good EMI(electromagnetic interference) shielding effect for the semiconductorchip 110 during operation.

Moreover, since both the power-connecting heat spreader 120 and theground-connecting heat spreader 130 are completely enclosed by theencapsulation body 150, they may not provide satisfactoryheat-dissipation efficiency for the packaged semiconductor chip 110.

SUMMARY OF THE INVENTION

An objective of this invention is to provide a semiconductor packagewith enhanced electrical and thermal performance, which provides goodEMI (electromagnetic interference) shielding effect.

Another objective of this invention is to provide a semiconductorpackage with enhanced electrical and thermal performance, by whichsatisfactory heat-dissipation efficiency is achieved.

A further objective of this invention is to provide a semiconductorpackage with enhanced electrical and thermal performance, wherein thesemiconductor package is cost-effectively fabricated.

In accordance with the above and other objectives, the present inventionproposes a BGA semiconductor package and a method for fabricating thesame.

The BGA semiconductor package of the invention comprises: a substratehaving a front surface and a back surface opposed to the front surface;at least a chip having an active surface and an inactive surface opposedto the active surface, wherein the active surface is formed with a powerplane and a ground plane, and the inactive surface is mounted on thefront surface of the substrate; a power-connecting heat spreader adaptedto entirely cover the chip, and electrically bonded to the front surfaceof the substrate and the power plane on the chip; a ground-connectingheat spreader positioned in elevation above the power-connecting heatspreader, and adapted to be electrically bonded to the front surface ofthe substrate and the ground plane on the chip; an encapsulation bodyfor encapsulating the front surface of the substrate, the chip, thepower-connecting heat spreader and the ground-connecting heat spreader;and a plurality of solder balls implanted on the back surface of thesubstrate.

The above package structure is characterized by the use of aspecially-designed set of power-connecting heat spreader andground-connecting heat spreader, which are each electrically connectedto and structured to entirely cover an underlying chip. Thereby, thepower-connecting heat spreader allows external power to be efficientlysupplied to the chip, and the ground-connecting heat spreader wouldprovide good EMI shielding effect for allowing the chip to improve itselectrical performance during operation. Further, a top surface of theground-connecting heat spreader is adapted to be exposed to outside ofan encapsulation body that encapsulates the chip, thereby helpingenhancing heat-dissipation efficiency for the package structure.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thefollowing detailed description of the preferred embodiments, withreference made to the accompanying drawings, wherein:

FIGS. 1A–1B (PRIOR ART) are schematic diagrams used to depict thestructure of a conventional BGA package; and

FIGS. 2A–2E are schematic diagrams used to depict a preferred embodimentof a semiconductor package of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following description is made with reference to FIGS. 2A–2E, fordetailing preferred embodiments of a BGA (ball grid array) semiconductorpackage proposed in the present invention.

As shown in FIG. 2E, the BGA semiconductor package of the inventioncomprises: a substrate 200 having a front surface 200 a and a backsurface 200 b opposed to the front surface 200 a; at least a chip 210having an active surface 210 a and an inactive surface 210 b opposed tothe active surface 210 a, wherein the active surface 210 a is formedwith a power plane 212 a and a ground plane 212 b, and the inactivesurface 210 b is mounted on the front surface 200 a of the substrate200; a power-connecting heat spreader 220 adapted to entirely cover thechip 210, and electrically bonded to the front surface 200 a of thesubstrate 200 and the power plane 212 a on the chip 210; aground-connecting heat spreader 230 positioned in elevation above thepower-connecting heat spreader 220, and adapted to be electricallybonded to the front surface 200 a of the substrate 200 and the groundplane 212 b on the chip 210; an encapsulation body 250 for encapsulatingthe front surface 200 a of the substrate 200, the chip 210, thepower-connecting heat spreader 220 and the ground-connecting heatspreader 230; and a plurality of solder balls 260 implanted on the backsurface 200 b of the substrate 200.

The above BGA semiconductor package can be fabricated by the followingsteps as illustrated in FIGS. 2A to 2E.

Referring to FIG. 2A, the first step is to prepare a substrate 200, achip 210, a power-connecting heat spreader 220, and a ground-connectingheat spreader 230.

The substrate 200 has a front surface 200 a and a back surface 200 b,with a plurality of power vias 201 a, ground vias 201 b and I/O(input/output) vias 201 c being formed to penetrate through thesubstrate 200.

The chip 210 has an active surface 210 a and an inactive surface 210 b.The active surface 210 a is formed with a plurality of power pads 211 a,ground pads 211 b and I/O pads 211 c. The active surface 210 a isfurther formed with a power plane 212 a and a ground plane 212 b,wherein the power plane 212 a is electrically connected to the powerpads 211 a by a first set of bonding wires 241 (shown in FIG. 2B), andthe ground plane 212 b is electrically connected to the ground pads 211b by a second set of bonding wires 242 (shown in FIG. 2B). Besides theuse of wire-bonding technology, other electrical connection methods,such as TAB (Tape Automatic Bond) technology, are also suitably adoptedfor electrically connecting the power plane 212 a and the ground plane212 b respectively to the power pads 211 a and the ground pads 211 b.

The power-connecting heat spreader 220 and the ground-connecting heatspreader 230 are each an integrally-formed piece ofelectrically-and-thermally conductive material, such as copper.

The power-connecting heat spreader 220 includes a support portion 221,an over-head portion 222 supported on the support portion 221, and adownward-extending portion 223 protruding downwardly from the overheadportion 222. The overhead portion 222 is formed with an opening 224, andsized in area to be equal to or slightly larger than the chip 210. And,the support portion 221 is formed with a plurality of mold-flow openings225.

The ground-connecting heat spreader 230 includes a support portion 231,an over-head portion 232 supported on the support portion 231, and adownward-extending portion 233 protruding downwardly from the overheadportion 232. The overhead portion 232 is sized in area to be equal to orslightly larger than the overhead portion 222 of the power-connectingheat spreader 220. And, the support portion 231 is formed with aplurality of mold-flow openings 234.

Referring FIG. 2B, the next step is to mount the chip 210 on the frontsurface 200 a of the substrate 200, wherein the power plane 212 a iselectrically connected to the power pads 211 a by the first set ofbonding wires 241, and the ground plane 212 b is electrically connectedto the ground pads 211 b by the second set of bonding wires 242. And, athird set of bonding wires 243 are formed for electrically connectingthe I/O pads 211 c on the chip 210 to the I/O vias 201 c of thesubstrate 200.

Referring further to FIG. 2C, the power-connecting heat spreader 220 ismounted over the front surface 200 a of the substrate 200 to entirelycover the chip 210 in a manner that, the support portion 221 iselectrically bonded to the power vias 201 a of the substrate 200, andthe downward-extending portion 223 is electrically connected to thepower plane 212 a on the chip 210, allowing the overhead portion 222 tobe elevated in position above the chip 210 by the support portion 221and the downward-extending portion 223, and not to interfere with thebonding wires 241, 242, 243.

Referring to FIG. 2D, the ground-connecting heat spreader 230 is mountedover the front surface 200 a of the substrate 200 to entirely cover thechip 210 in a manner that, the support portion 231 is bonded to theground vias 201 b of the substrate 200, and the downward-extendingportion 233 penetrates through the opening 224 of the power-connectingheat spreader 220 to be electrically bonded to the ground plane 212 b onthe chip 210, allowing the overhead portion 232 to be elevated inposition above the power-connecting heat spreader 220 by the supportportion 231 and the downward-extending portion 233.

Referring to FIG. 2E, a molding process is performed to form anencapsulation body 250 that encapsulates the front surface 200 a of thesubstrate 200, the chip 210, the power-connecting beat spreader 220, andthe ground-connecting heat spreader 230. During molding, a moldingcompound used for forming the encapsulation body 250 would flow throughthe mold-flow openings 225, 234 at the support portions 221, 231 of thepower-connecting heat spreader 220 and ground-connecting heat spreader230 respectively, whereby the chip 210 can be assured to be entirelyencapsulated by the molding compound. It is preferable to adapt theoverhead portion 232 of the ground-connecting heat spreader 230 to beexposed to outside of the encapsulation body 250, thereby helpingincrease heat-dissipation efficiency for the package structure.

Then, a plurality of solder balls 260 are implanted on the back surface200 b of the substrate 200, including power balls 261 electricallyconnected to the power vias 201 a, ground balls 262 electricallyconnected to the ground vias 201 b, and I/O balls 263 electricallyconnected to the I/O vias 201 c. This therefore completes thefabrication of the BGA package of the invention.

By the above fabricated package structure illustrated in FIG. 2E, powercan be externally supplied to the chip 210 successively via the powerballs 261, the power vias 201 a, the power-connecting heat spreader 220,the power plane 212 a, the bonding wires 241, and the power pads 211 a.Moreover, the chip 210 can be connected to ground successively via theground pads 211 b, the bonding wires 242, the ground plane 212 b, theground-connecting heat spreader 230, the ground vias 201 b, and theground balls 262. Further, the chip 210 can transfer I/O signals via theI/O pads 211 c, the bonding wires 243, the I/O vias 201 c, and the I/Oballs 263.

Besides power transmission and grounding effect, the power-connectingheat spreader 220 and the ground-connecting heat spreader 230 also helpenhance heat dissipation for the packaged chip 210, and thus improveoverall heat-dissipation efficiency of the package structure.

Compared to the package structure in the prior art of FIGS. 1A–1B, theBGA package of the invention has the following advantageous.

First, as the ground connecting heat spreader 230 of the invention isarranged to entirely cover the chip 210, it can provide better EMI(electromagnetic interference) shielding effect for allowing the chip210 to improve its electrical performance during operation.

Further, as the overhead portion 232 of the ground-connecting heatspreader 230 of the invention is exposed to outside of the encapsulationbody 250 that encapsulates the chip 210, better heat-dissipationefficiency is effected for the BGA package of the invention.

Moreover, as the power-connecting heat spreader 220 of the inventionentirely covering the chip 210 is sized to be much larger than the priorart of using a power-connecting heat spreader only covering part of achip, thereby power from an external source can be more efficientlysupplied to the chip 210 in the invention.

The invention has been described using exemplary preferred embodiments.However, it is to be understood that the scope of the invention is notlimited to the disclosed embodiments. On the contrary, it is intended tocover various modifications and similar arrangements. The scope of theclaims, therefore, should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A method for fabricating a semiconductor package, comprising thesteps of: preparing a substrate having a front surface and a backsurface opposed to the front surface, wherein a plurality of I/O(input/output) vias, power vias and ground vias are formed to extendfrom the front surface to the back surface of the substrate; mounting atleast a chip having an active surface and an inactive surface opposed tothe active surface, wherein the active surface is formed with aplurality of I/O pads, power pads and ground pads, and further formedwith a power plane and a ground plane in a manner that, the power planeis electrically connected to the power pads, and the ground plane iselectrically connected to the ground pads, and wherein the inactivesurface of the chip is mounted on the front surface of the substrate;forming a plurality of bonding wires for electrically connecting the I/Opads on the chip to the I/O vias of the substrate; mounting apower-connecting heat spreader over the front surface of the substrate;the power-connecting heat spreader having a support portion, an overheadportion supported on the support portion, and a downward-extendingportion protruding downwardly from the overhead portion, wherein thesupport portion is electrically bonded to the power vias of thesubstrate, and the downward-extending portion is electrically bonded tothe power plane on the chip, allowing the overhead portion to beelevated in position above the chip by the support portion and thedownward-extending portion in a manner that, the power-connecting heatspreader entirely covers the chip; mounting a ground-connecting heatspreader over the front surface of the substrate; the ground-connectingheat spreader having a support portion, an overhead portion supported onthe support portion, and a downward-extending portion protrudingdownwardly from the overhead portion, wherein the support portion iselectrically bonded to the ground vias of the substrate, and thedownward-extending portion is electrically bonded to the ground plane onthe chip, allowing the overhead portion to be elevated by the supportportion and the downward-extending portion in position above theoverhead portion of the power-connecting heat spreader in a manner that,the ground-connecting heat spreader entirely covers the chip; forming anencapsulation body for encapsulating the front surface of the substrate,the chip, the power-connecting heat spreader and the ground-connectingheat spreader; and implanting a plurality of solder balls on the backsurface of the substrate, and electrically bonding the solder balls tothe vias.
 2. The method of claim 1, wherein the power plane and theground plane are electrically connected respectively to the power padsand the ground pads by means of wire-bonding technology.
 3. The methodof claim 1, wherein the power plane and the ground plane areelectrically connected respectively to the power pads and the groundpads by means of TAB (tape automated bonding) technology.
 4. The methodof claim 1, wherein the power-connecting heat spreader and theground-connecting heat spreader are each an integrally-formed piece ofelectrically-and-thermally conductive material.
 5. The method of claim1, wherein the overhead portion of the power-connecting heat spreader isformed with an opening, for allowing the downward-extending portion ofthe ground-connecting heat spreader to penetrate through the opening andto be electrically bonded to the ground plane on the chip.
 6. The methodof claim 1, wherein the support portion of the power-connecting heatspreader and the support portion of the ground-connecting heat spreaderare each formed with at least an opening, for allowing a moldingcompound used for forming the encapsulation body to pass through theopening.
 7. The method of claim 1, wherein the overhead portion of theground-connecting heat spreader is exposed to outside of theencapsulation body.